A VLSI Architecture for a High-Speed All-Digital Quadrature Modulator and Demodulator for Digital Radio Applications

Abslruer-An all-digital architecture is presented for implementing the front-end signal processing functions in a quadrature modulator and demodulator for high bit-rate digital radio applications. A pair of CMOS chips has been designed and submitted for fabrication in a 1.25 pm process and is expected to accommodate symbol rates up to 35 MBd. The modulator chip accepts a pair of 8 b in-phase and quadrature data streams and generates a bandlimited IF output with an excess bandwidth factor of 35%. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. Clock and carrier recovery must be performed external to the demodulator chip. The modulator and demodulator chips each incorporate 40-tap multiplierless FIR square-root Nyquist matched filters and the cascade of the two chips achieves a peak intersymbol interference distortion of -54 dB (assuming ideal D/A and A/D conversion). The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256 X 256 points, thus, the all-digital implementation results in a generic chip set suitable for a wide variety of high bit-rate digital modem designs using various modulation formats such as M-ary PSK and QAM.